Why Post-Quantum Cryptography Must Start at the Hardware Level
Software-only PQC migration falls short in embedded systems. Here's why quantum-resistant security must be built at the silicon level.
Side-Channel Attacks on PQC: What Hardware Engineers Need to Know
Mathematically secure doesn't mean implementation-secure. Lattice-based PQC is vulnerable to power analysis and EM attacks — and only hardware can fix it.
PoSyn: A Graphical Approach Towards Side-Channel Aware Synthesis
Graphical approach for integrating side-channel resistance into the hardware synthesis flow.
amisha-srivastava
STBC: Side-channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay
Balanced circuit design methodology for side-channel resistance with reduced propagation delay.
Binary Decision Diagram to Design Balanced Secure Logic Styles
BDD-based methodology for designing side-channel resistant balanced logic circuits.
Mutual Information Analysis for Three-Phase Dynamic Current Mode Logic against Side-Channel Attack
Mutual information analysis evaluating three-phase dynamic current mode logic against side-channel attacks.
Three Phase Dynamic Current Mode Logic: A More Secure DyCML to Achieve a More Balanced Power Consumption
Three-phase DyCML design for balanced power consumption and enhanced side-channel resistance. **Best Paper Award.**