Why Post-Quantum Cryptography Must Start at the Hardware Level
Software-only PQC migration falls short in embedded systems. Here's why quantum-resistant security must be built at the silicon level.
Side-Channel Attacks on PQC: What Hardware Engineers Need to Know
Mathematically secure doesn't mean implementation-secure. Lattice-based PQC is vulnerable to power analysis and EM attacks — and only hardware can fix it.
Drone Security: Why UAVs Need Silicon-Level Protection
Software security isn't enough for UAVs. Drones need hardware-level protection against GPS spoofing, firmware tampering, and communication hijacking.
SymbFuzz: Symbolic Execution Guided Hardware Fuzzing
Symbolic execution guided hardware fuzzing for deeper vulnerability detection in hardware designs.
samit-shahnawaz-miftah
InterConFuzz: A Fuzzing-based Comprehensive NoC Verification Framework
Fuzzing-based verification framework for Network-on-Chip security and functional validation.
samit-shahnawaz-miftah
PoSyn: A Graphical Approach Towards Side-Channel Aware Synthesis
Graphical approach for integrating side-channel resistance into the hardware synthesis flow.
amisha-srivastava