STBC: Side-channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay
Jul 1, 2017·
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0 min read
James Hyunmin Kim
Seokhie Hong
Bart Preneel
Ingrid Verbauwhede
Abstract
This paper presents STBC, a side-channel attack tolerant balanced circuit design methodology that achieves reduced propagation delay while maintaining strong resistance against power analysis attacks. The approach balances power consumption across all logic transitions without incurring significant timing overhead.
Type
Publication
In IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017)
Authors
James Hyunmin Kim
(he/him)
Senior SoC Architect & Hardware Security Expert
Ph.D. in Electrical Engineering from KU Leuven (imec-COSIC), with 15+ years of expertise
in secure SoC architecture, hardware security, and cryptographic implementations.
Specialized in ARM/RISC-V security subsystems, side-channel countermeasures, and
post-quantum cryptography. 4 silicon tape-outs, CAVP-certified security IPs.