SMART DShot: Secure Machine-Learning-Based Adaptive Real-Time Timing Correction
Jun 1, 2025·
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0 min read
James Hyunmin Kim
Z.B. Shaik Kadu
Kyusuk Han
Abstract
This paper presents SMART DShot, a secure machine-learning-based adaptive real-time timing correction protocol for electronic speed controllers. The proposed system implements a bidirectional DShot protocol (150/300/600/1200) with an FPGA-based ML engine featuring feature extraction and neural network inference for ESC timing error correction, enabling robust and reliable communication in safety-critical embedded systems.
Type
Publication
Applied Science Journal
Authors
James Hyunmin Kim
(he/him)
Senior SoC Architect & Hardware Security Expert
Ph.D. in Electrical Engineering from KU Leuven (imec-COSIC), with 15+ years of expertise
in secure SoC architecture, hardware security, and cryptographic implementations.
Specialized in ARM/RISC-V security subsystems, side-channel countermeasures, and
post-quantum cryptography. 4 silicon tape-outs, CAVP-certified security IPs.