Hardware-Enforced Trust Chain

Aug 1, 2025 · 1 min read
projects

A hardware-enforced trust chain architecture with formal verification for secure boot and key management lifecycle. The project leverages Z3 SMT Solver to formally verify security properties of the boot chain, ensuring that each stage of the boot process is cryptographically authenticated before execution.

Key contributions:

  • Formal verification framework for secure boot sequences using Z3 SMT Solver
  • Key management lifecycle with hardware-backed key storage and rotation
  • ML-based runtime validation for continuous trust chain integrity monitoring
  • Integration with ARM and RISC-V security subsystems

This work was conducted at the Technology Innovation Institute (TII) as part of the Secure Systems Research Centre’s mission to build verifiably secure embedded platforms.

Secure Boot Trust Chain Formal Verification Key Management
James Hyunmin Kim
Authors
James Hyunmin Kim (he/him)
Senior SoC Architect & Hardware Security Expert
Ph.D. in Electrical Engineering from KU Leuven (imec-COSIC), with 15+ years of expertise in secure SoC architecture, hardware security, and cryptographic implementations. Specialized in ARM/RISC-V security subsystems, side-channel countermeasures, and post-quantum cryptography. 4 silicon tape-outs, CAVP-certified security IPs.