Security Subsystem Architecture
Dec 1, 2023
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1 min read
A comprehensive security subsystem architecture for ARM/RISC-V CPU-based SoC platforms, encompassing power, clock, and reset management alongside a Safety Island architecture for mixed-criticality applications.
Key contributions:
- Security Architecture Lead for ARM/RISC-V CPU-based Security Subsystem at TII
- Power/Clock/Reset Management architecture with security-aware sequencing
- Safety Island Architecture for functional safety integration
- Led open-source SoC design project (Al Saqr) based on OpenTitan Root of Trust
- Bus Level Security (BLS) implementation for on-chip access control
This architecture forms the foundation of TII’s secure SoC platform, providing hardware-enforced isolation, secure boot, and cryptographic services for autonomous systems and defense applications.
Authors
James Hyunmin Kim
(he/him)
Senior SoC Architect & Hardware Security Expert
Ph.D. in Electrical Engineering from KU Leuven (imec-COSIC), with 15+ years of expertise
in secure SoC architecture, hardware security, and cryptographic implementations.
Specialized in ARM/RISC-V security subsystems, side-channel countermeasures, and
post-quantum cryptography. 4 silicon tape-outs, CAVP-certified security IPs.