ML-Powered DShot Protocol (SMART DShot)
Jan 1, 2025
·
1 min read
SMART DShot is a secure machine-learning-based adaptive real-time timing correction system for Electronic Speed Controllers (ESC). The project implements a bidirectional DShot protocol supporting 150/300/600/1200 baud rates with an FPGA-based ML inference engine.
Key contributions:
- Bidirectional DShot protocol implementation (150/300/600/1200) on FPGA
- Feature extraction pipeline for real-time timing signal analysis
- Neural network inference engine for adaptive timing error correction
- Published in Applied Science Journal, 2025
The ML engine performs on-device inference to detect and correct timing errors in real-time, enabling reliable ESC communication in safety-critical drone and robotics applications.
Authors
James Hyunmin Kim
(he/him)
Senior SoC Architect & Hardware Security Expert
Ph.D. in Electrical Engineering from KU Leuven (imec-COSIC), with 15+ years of expertise
in secure SoC architecture, hardware security, and cryptographic implementations.
Specialized in ARM/RISC-V security subsystems, side-channel countermeasures, and
post-quantum cryptography. 4 silicon tape-outs, CAVP-certified security IPs.