Security Architecture Lead for ARM/RISC-V CPU-based Security Subsystem. Developed secure boot, key management with formal verification (Z3 SMT Solver). Led open-source SoC project (Al Saqr) based on OpenTitan RoT. Conducted fault injection and side-channel analysis on i.MX93, PolarFire SoC, and Nvidia Orin.
Associate Staff Digital Design Engineer
Silicon Laboratories International
Security Subsystem Design Lead with Bus Level Security (BLS). Enhanced ARM TrustZone integration with crypto hardware accelerators. Designed custom crypto engines with EFUSE controller.
Secure & Safe RISC-V Program Manager / Senior R&D Engineer
Secure-IC
RISC-V International representative and technical lead. Supervised 2 Ph.D. candidates at Telecom Paris. Developed dual-core lockstep for automotive safety (Patent pending). ISO 26262, ISO/SAE 21434, FIPS 140-2/3 compliance.
Senior ASIC Digital Design Engineer, Security IP
Synopsys Canada ULC
Led DWC TRNG/NIST TRNG development achieving CAVP certification. Developed Inline Memory Encryption (AES-XTS) and PQC cryptographic modules. SCA countermeasures with FIPS 140-2/3, BSI AIS 31, OSCCA compliance.
Secure Hardware Engineer
NXP Laboratories Ltd.
Owner of all block cipher IPs in NXP. Designed threshold implementations and SCA/FA countermeasures. Developed scalable ECDSA/ECC IPs (5 NIST prime curves) and lightweight crypto IPs.
Process Engineer
Samsung Semiconductor
Lithography Division with SEM and FIB expertise.
Education
Ph.D. in Electrical Engineering
KU Leuven, imec-COSIC (Belgium)
Thesis: “Side-channel security by design: Hardware level countermeasures”
Supervisors: Prof. Bart Preneel, Prof. Ingrid Verbauwhede | Co-promotor: Prof. Seokhie Hong.
4 MPW tape-outs (AES, RSA, ECC, PRESENT). Best Paper Award at WISA 2012.
M.Sc. in Information Security and Applied Cryptographic Engineering
Korea University (South Korea)
GPA: 93.8%. Korea crypto library design (Klib). Research on SNR ratio improvement using signal processing.
Technical Skills
Hardware Design
VHDL / Verilog / SystemVerilog
ASIC/FPGA Design
RTL to Tape-out
UVM Verification
Security
Side-Channel Analysis (SCA/FIA)
Post-Quantum Cryptography
ARM TrustZone / RISC-V
FIPS 140-2/3 Compliance
Programming
C/C++
Python
Perl / Tcl
MATLAB / Sage
Awards & Certifications
Patent Pending — Single Core Lockstep
Secure-IC ∙
January 2022
Dual-core lockstep architecture for automotive safety applications.
CAVP Certification — TRNG Development
NIST ∙
October 2019
Led DWC TRNG/NIST TRNG development achieving CAVP certification at Synopsys.
Best Paper Award
WISA 2012 ∙
August 2012
Three Phase Dynamic Current Mode Logic: A More Secure DyCML to Achieve a More Balanced Power Consumption