SymbFuzz: Symbolic Execution Guided Hardware Fuzzing
Symbolic execution guided hardware fuzzing for deeper vulnerability detection in hardware designs.
samit-shahnawaz-miftah
🔐James Hyunmin Kim
(he/him)
Senior SoC Architect & Hardware Security Expert
Professional Summary
Ph.D. in Electrical Engineering from KU Leuven (imec-COSIC), with 15+ years of expertise
in secure SoC architecture, hardware security, and cryptographic implementations.
Specialized in ARM/RISC-V security subsystems, side-channel countermeasures, and
post-quantum cryptography. 4 silicon tape-outs, CAVP-certified security IPs.
Education
Ph.D. in Electrical Engineering
KU Leuven, imec-COSIC (Belgium)
M.Sc. in Information Security and Applied Cryptographic Engineering
Korea University (South Korea)
Interests
Post-Quantum Cryptography
Side-Channel Analysis & Countermeasures
Secure SoC Architecture
Hardware Root of Trust
Trusted Execution Environments
Formal Verification of Security Properties
Research Focus
My research bridges the gap between theoretical cryptography and silicon-level implementation, with a focus on building verifiably secure hardware systems for the post-quantum era.
Current research areas:
- Hardware-Enforced Trust Chains — Formal verification of secure boot and key management using SMT solvers, with ML-based runtime validation
- Post-Quantum Cryptography Hardware — PQC IP development and vulnerability analysis in ARM TrustZone TEEs
- Side-Channel Secure Design — From balanced circuit methodologies (3P-DyCML, STBC) to SCA-aware synthesis flows
- Hardware Security Verification — Fuzzing-based frameworks (InterConFuzz, SymbFuzz) and LLM-powered assertion optimization for hardware validation
Featured Publications
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InterConFuzz: A Fuzzing-based Comprehensive NoC Verification Framework
Fuzzing-based verification framework for Network-on-Chip security and functional validation.
samit-shahnawaz-miftah
SMART DShot: Secure Machine-Learning-Based Adaptive Real-Time Timing Correction
ML-powered bidirectional DShot protocol with FPGA-based neural network for real-time ESC timing correction.
Three Phase Dynamic Current Mode Logic: A More Secure DyCML to Achieve a More Balanced Power Consumption
Three-phase DyCML design for balanced power consumption and enhanced side-channel resistance. **Best Paper Award.**
Recent Publications
(2025).
SymbFuzz: Symbolic Execution Guided Hardware Fuzzing.
MICRO 2025.
(2025).
InterConFuzz: A Fuzzing-based Comprehensive NoC Verification Framework.
DAC 2025.
(2025).
SMART DShot: Secure Machine-Learning-Based Adaptive Real-Time Timing Correction.
Applied Science.
(2025).
PoSyn: A Graphical Approach Towards Side-Channel Aware Synthesis.
IEEE TVLSI (Under Review).
(2024).
Assert-O: Context-based Assertion Optimization using LLMs.
GLSVLSI 2024.
Blog
Building a Hardware Root of Trust: From Secure Boot to TEE
A comprehensive look at how modern SoCs build trust from the first instruction — Boot ROM, Secure Boot, Measured Boot, and Trusted Execution Environments.
Drone Security: Why UAVs Need Silicon-Level Protection
Software security isn't enough for UAVs. Drones need hardware-level protection against GPS spoofing, firmware tampering, and communication hijacking.
KCMVP 3.0 Changes: What Korean Semiconductor Companies Need to Prepare
Korea's cryptographic module validation program is evolving for the post-quantum era. Here's what semiconductor companies need to know and prepare.
Side-Channel Attacks on PQC: What Hardware Engineers Need to Know
Mathematically secure doesn't mean implementation-secure. Lattice-based PQC is vulnerable to power analysis and EM attacks — and only hardware can fix it.
Why Post-Quantum Cryptography Must Start at the Hardware Level
Software-only PQC migration falls short in embedded systems. Here's why quantum-resistant security must be built at the silicon level.